Open mattvenn opened 1 year ago
seems that the old style of port definition is no longer supported
output user2_vcc_powergood,
output user1_vdd_powergood,
output user2_vdd_powergood
);
wire [462:0] mprj_logic1;
wire mprj2_logic1;
wire mprj_vdd_logic1_h;
wire mprj2_vdd_logic1_h;
wire mprj_vdd_logic1;
wire mprj2_vdd_logic1;
wire user1_vcc_powergood;
wire user2_vcc_powergood;
wire user1_vdd_powergood;
wire user2_vdd_powergood;
@mattvenn : I expect it is supported, but it may be that it now requires a specific switch. Check the iverilog
documentation for command-line options for supported verilog styles (also check if there are any "release notes" with iverilog 13 that would suggest that such a change was implemented).
I recently hit this, and bisected it to https://github.com/steveicarus/iverilog/commit/6204b78610fedbe36b73fd26bf144f2f07849fb3
The commit mentions:
(System)Verilog allows to declare the port direction separate from the
signal declaration. E.g.
output x;
integer x;
But this is only allowed if the port declaration
* does not have an explicit net type
* does not have an explicit data type
* is a non-ANSI style declaration
For all other cases of port declarations the signal is considered fully
defined and it is not allowed to have a separate signal declaration.
Assuming this falls under the non-ANSI style declaration, then it appears to be an Icarus Verilog issue.
I submitted a caravel fix: https://github.com/efabless/caravel/pull/403
lots of errors like these: