Modified the HDL hierarchy of caravan to be consisting of caravan_core and chip_io_alt

efabless / caravel

Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.

https://caravel-harness.readthedocs.io/

Apache License 2.0

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Closed mo-hosni closed 1 year ago

mo-hosni commented 1 year ago

added verilog/rtl/caravan_core.v and modified the hierarchy in verilog/rtl/caravan.v to be consisting of caravan_core and chip_io_alt
removed buff_flash_clkrst
removed all pathrus
added porb_l connection to caravel_clocking
added (* keep *) to spare_logic_block