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efabless / caravel

Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.
https://caravel-harness.readthedocs.io/
Apache License 2.0
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mpw-9: user id bits reversed in gl verilog and layout. #516

Closed d-m-bailey closed 10 months ago

d-m-bailey commented 11 months ago

For example, the rtl parameter in caravel_core.v is set to 

    parameter USER_PROJECT_ID = 32'h23117f7b;

which is 0010_0011_0001_0001_0111_1111_0111_1011 However, the gl verilog and layout have the bits reversed because the id is split into a python array which indexes from 0 at the left most bit. This results in the reversed value 1101_1110_1111_1110_1000_1000_1100_0100.

RTimothyEdwards commented 11 months ago

So scripts/set_user_id.py just needs line 173 to be user_id_bits = '{0:032b}'.format(user_id_int)[::-1]?