mgmt GPIO registers have 32 bits, shouldn't it only be 1 bit?
reg_mprj_io_xx definitions has some ambiguous bits
bit 2 | hold state value | Value of GPIO when in low-power state. @RTimothyEdwards mentioned that this should be removed
bit 5,6,7 | analog enable/select/polarity @RTimothyEdwards mentioned they should be removed as they're probably not functioning correctly because we do not have the vswitch enable bit set on the pads
IRQ has 32 bit registers, shouldn't they be 1 bit? Registers also need to have better documentation
There are some unclear register definitions in https://github.com/efabless/caravel/blob/main/docs/caravel_datasheet_2_register_TRM_r2.pdf
mgmt GPIOregisters have 32 bits, shouldn't it only be 1 bit?reg_mprj_io_xxdefinitions has some ambiguous bitsbit 2 | hold state value | Value of GPIO when in low-power state.@RTimothyEdwards mentioned that this should be removedbit 5,6,7 | analog enable/select/polarity@RTimothyEdwards mentioned they should be removed as they're probably not functioning correctly because we do not have the vswitch enable bit set on the padsIRQhas 32 bit registers, shouldn't they be 1 bit? Registers also need to have better documentation