Some gate-level netlists in verilog/gl/ were changed after deletion of excessive decap_12 cells, but the way the files were rewritten to use Verilog instance arrays is not fully compatible with the caravel_user_project (and other) full-chip STA flows.
Some gate-level netlists in
verilog/gl/were changed after deletion of excessive decap_12 cells, but the way the files were rewritten to use Verilog instance arrays is not fully compatible with the caravel_user_project (and other) full-chip STA flows.For more information, see: https://github.com/efabless/caravel_user_project/issues/377