`docs/caravel_datasheet.pdf` says PicoRV32

[mithro]

The datasheet @ https://github.com/efabless/caravel_board/blob/main/docs/caravel_datasheet.pdf says;

The Caravel harness comprises a small RISC-V microprocessor based on the simple 2-cycle PicoRV32 RISC-V core implementing the RV32IMC instruction set (see http://riscv.org/).

The processor core is the PicoRV32 design (see http://github.com/cliffordwolf/picorv32). The full core description is available from the github site. The hardware implementation is the “large” variant, incorporating options IRQ, MUL, DIV, BARREL_SHIFTER, and COMPRESSED_ISA (16-bit instructions).

I'm guessing this is all wrong?

[jeffdi]

Will update.