M0stafaRady
commented
1 year ago @jeffdi this issue this exist because the new RTL change is using assign cs_b = (~core_rstn); instead of assign cs_b = (core_rstn);
this need to be inverted somewhere I inverted the signal inside the sram module. Please merge https://github.com/efabless/caravel_mgmt_soc_gf180mcu/pull/12
New litex generation disables writing to sram. Changing the chip select signal form
assign sram_cs_b = core_rstn;toassign cs_b = 1'd0;is why it fails. Assigning it to 0 are wrong because the memory have signal namedcen_fellthat would be 1 when chip select value flips from 1 to 0.