From the previous announcements it looks like the management soc in mpw-2,3,4 has been swapped out with the litex version. For pre-mpw-4 projects we ran our DV with the previous picorv32 which had a mask of 32'hff000000 vs the new smaller mask.
I haven't had a chance to rerun my DV tests with the new soc to confirm. Hopefully I'm just misunderstanding the litex design and this isn't actually a problem that will impact projects.
In https://github.com/efabless/caravel_mgmt_soc_litex/blob/c741d6145024e621dc10b7f511a306e4858a92f9/litex/caravel.py#L186 the defined mprj size is much smaller than the original management soc mprj memory region.
From the previous announcements it looks like the management soc in mpw-2,3,4 has been swapped out with the litex version. For pre-mpw-4 projects we ran our DV with the previous picorv32 which had a mask of 32'hff000000 vs the new smaller mask.
My project (mpw-3 randsack) probably won't work with the new soc: https://github.com/harrisonpham/randsack/blob/7f024646f327b8cfc0e80fef52505b4bfa8bc87a/ip/randsack/rtl/digitalcore_macro.v#L68
I haven't had a chance to rerun my DV tests with the new soc to confirm. Hopefully I'm just misunderstanding the litex design and this isn't actually a problem that will impact projects.