Update Litex mgmt soc

[tmichalak]

This PR updates the litex mgmt core and locks the submodules the core is generated from. The list of changes is as follows:

• Added dependencies as Git submodules for version locking
• Replaced deprecated LiteX calls
• Removed support for obsolete SPIFlash controller
• Added script arguments for CPU selection, software compilation flag and platform
• Updated the mgmt_core module
• Cleaned up the Makefile and added targets for updating the mgmt_core and generating the software headers

[shalan]

@tmichalak 1) LiteX generated Verilog HDL contains inline initializations for several registers. These initializations are not ASIC friendly. In ASIC they have to be initialized using a Reset signal. In the older version of the management SoC, we modified the generated Verilog code to fix this issue. I think this has to be addressed in LiteX itself. 2) Is the new debug interface fully functional? Was it FPGA validated? We are not able to get to work.

[tmichalak]

@shalan Can you give an example of these manual changes? However it would be best to address these issues in Litex's code instead of the generated code. The PR that targets the Arty board is still WIP, but we were able to generate a valid bitstream that can drive selected GPIOs (run the blink example from https://github.com/efabless/caravel_board).

[shalan]

@tmichalak Please check: https://github.com/efabless/caravel_mgmt_soc_litex/blob/main/verilog/rtl/mgmt_core.w_rst_init_modification.v

Regarding the new debug bridge, I understand that it is not yet FPGA validated. Was it verified in simulation? Also, is there any documentation for how to use it with gdb?

[jeffdi]

@shalan @tmichalak There is a script that makes these changes. See https://github.com/efabless/caravel_mgmt_soc_litex/blob/main/litex/modify_verilog.py

[mithro]

FYI - Depending on what you mean by "the debug interface", I'm 100% sure it has been used by multiple different groups both on FPGAs and in simulations.

The Fomu workshop has an example of using it @ https://workshop.fomu.im/en/latest/riscv.html#debugging-risc-v-code

There is also a whole section on co-simulation scenarios with Renode @ https://workshop.fomu.im/en/latest/renode.html

There is a page which has even more documentation at https://github.com/enjoy-digital/litex/wiki/Use-GDB-with-VexRiscv-CPU

There is also this pretty good blog post from Tom -> https://tomverbeure.github.io/2021/07/18/VexRiscv-OpenOCD-and-Traps.html