Constructs unsupported for synthesis

[mo-hosni]

The declaration of regs as

reg x = 1'b1;

such as in https://github.com/efabless/caravel_mgmt_soc_litex/blob/3222bd57445eb6e734f010b9bed369b53c6066fe/verilog/rtl/mgmt_core.v#L150 isn't supported in ASIC synthesis. This is equivalent to

reg mgmtsoc_vexriscv;
initial 
    mgmtsoc_vexriscv = 32'd268435456;

So, the initial part is ignored by synthesis tools such as DC. This didn't cause an issue with yosys but I don't think it is correct. A simple fix would be converting the reg to a wire so it's an assign statement which is synthesizable. I did that for the mgmtsoc_vexriscv to get the GL from DC to work. But still, this error is in the HDL in around 1800 different lines.

[mo-hosni]

@jeffdi