mprj wishbone address range is limited to 0x3010_0000 instead of 0x3fff_ffff

[mattvenn]

https://github.com/efabless/caravel_mgmt_soc_litex/blob/3fee299f8177cebf7919eb0e6da7f0f5ad7af31d/litex/caravel.py#L186

[mattvenn]

@suppamax said:

(Here)[https://caravel-harness.readthedocs.io/en/latest/memory-mapped-io-summary.html] a wishbone base address is mentioned: should I add a "wishbone last addr" field?

I cannot find a wishbone-related documentation in the management SoC repo (and it looks like there is no readthedocs page yet).

Those docs are out of date from when caravel contained the cpu as well. Now this repo contains the litex management soc containing the cpu so this repo should generate the docs. You can see them in https://github.com/efabless/caravel_mgmt_soc_litex/tree/main/docs/generated

so far they don't have a readthedocs (also needs to get done).

RE your question, I'd say yes, either an end address or a width would work.

[suppamax]

Do I understand it correctly - the idea is to

1. extend that outdated document with the warning (size or end addr)
2. consolidate the documentation for caravel_mgmt_soc_litex

[mattvenn]

I think leave the docs stuff for me. The idea is we will have at least 2 repos providing docs for caravel:

• caravel which contains, gpios, the management protection, spi stuff
• litex (this repo) that contains everything inside the managment soc, which would include wishbone, memory maps. etc.

Make sense?

[egorxe]

May be it would be better to extend this address space for future MPWs in addition to documenting it? 1 MByte may be not enough for some projects (SDRAM/HyperRAM controllers for example) and there seems to be no reason why it could not be extended up to previous size (256 MBytes). Currently this address space is empty anyway.

[clp510]

is there any update on this bug ?

[suppamax]

@clp510 the last information I got are here The code should have been fixed, there is a PR for a dedicated test, I don't know about the documentation.

[jeffdi]

duplicates issue #10