Open suppamax opened 2 years ago
When I run make setup from litex, the generated mgmt_core.v has signals declared twice. The reason is that verilog._print_signals is not overwritten in caravel_platform.py and signals are declared also via _new_print_module
make setup
litex
mgmt_core.v
verilog._print_signals
caravel_platform.py
_new_print_module
When I run
make setupfromlitex, the generatedmgmt_core.vhas signals declared twice. The reason is thatverilog._print_signalsis not overwritten incaravel_platform.pyand signals are declared also via_new_print_module