Cannot access housekeeping register for SPI and SYS

[devsaurus]

Description

I want to configure the PLL with software from CPU side. The respective registers are located in housekeeping in the 0x261000xx address range. Ref https://github.com/efabless/caravel/blob/44a83f90eb5dbfb8fd620c2f61bf0777a231ddcf/verilog/rtl/housekeeping.v#L59

Expected result

Writing to the PLL divider register (0x26100024) and others works.

Observed result

When writing to 0x26100024, the wishbone access is not acknowledged and the CPU stalls infinitely.

Additional information

As far as I understand, the access is outside of the defined region for housekeeping. Ref size parameter at https://github.com/efabless/caravel_mgmt_soc_litex/blob/fff888c4b5167ddd73689f153209555627eb8a8e/litex/caravel.py#L200

This restricts access to housekeeping's 0x260xxxxx range and blocks access to its SPI and SYS ranges at 0x261xxxxx and 0x262xxxxx, respectively.

[jeffdi]

This is confirmed with the sysctl testbench.