The two modules for the SRAM and the VexRISC core do not have power supply pin connections matching all the other modules. These should be in #fidef USE_POWER_PINS ... #endif blocks.
Short-term fix: Correct the mgmt_core verilog to add the ifdef block
Long-term fix: Correct the upstream LiteX file that generated the code in the first place.
The two modules for the SRAM and the VexRISC core do not have power supply pin connections matching all the other modules. These should be in
#fidef USE_POWER_PINS
...#endif
blocks.Short-term fix: Correct the mgmt_core verilog to add the ifdef block
Long-term fix: Correct the upstream LiteX file that generated the code in the first place.