Closed jeffdi closed 2 years ago
Changes to correct wb address issues for the user project and housekeeping. Also correct duplicate assign statements in the verilog as well as adds power pins for SRAM and VexRiscv.
Several testbenches also added.
Fixes issue #10 , #45 , #38 , #46
Changes to correct wb address issues for the user project and housekeeping. Also correct duplicate assign statements in the verilog as well as adds power pins for SRAM and VexRiscv.
Several testbenches also added.
Fixes issue #10 , #45 , #38 , #46