Closed M0stafaRady closed 1 year ago
Determined to be a test configuration issue. Testbench now passes.
The read from reg_uart_data needs to be followed by the uart_ev_pending register.
uart_ev_pending_write(UART_EV_RX);
The bit order for sending data to the UART was reversed.
Screenshot of successful simulation waveform.
I'm developing test (uart_rx.py uart_rx.c) to send more than 1 character to UART. However register :ref:
UART_RXTX <UART_RXTX>
doesn't clear when reading from it as expected. I can't find a way to pass the first character and check the following ones.Is there a way to clear :ref:
UART_RXTX <UART_RXTX>
so firmware can see the other characters, or in other word, how to pop the fifo first element so the next character can be read by the firmware?