generated mgmt_soc and dffram cell name and interface mismatch

[kareefardi]

New dffram cells has the following interface

 input CLK;
 input EN0;
 input VGND;
 input VPWR;
 input [7:0] A0;
 input [31:0] Di0;
 output [31:0] Do0;
 input [3:0] WE0;

The generated interface in mgmt_soc doesn't have a 0 postfix. In addition, cell names should be RAM128 and RAM256 for the 512B and the 1KB as these are the outputs from the dffram generator

[kareefardi]

commits ee316545117895812aa72d5de82192d5e2e6f4e8 and 62ee723241c198eb432ee16bb7b61836d6452f4a regenerates DFFRAM while renaming it and adhering to the interface stated above