clean up unused files

[proppy]

is https://github.com/efabless/caravel_user_project/blob/main/verilog/rtl/uprj_netlists.v still used?

[proppy]

similarly are files in https://github.com/efabless/caravel_user_project/tree/main/verilog/includes still used? (they don't seem to be using a consistent syntax)

[marwaneltoukhy]

similarly are files in https://github.com/efabless/caravel_user_project/tree/main/verilog/includes still used? (they don't seem to be using a consistent syntax)

Yes they are used in simulation, they have inconsistent syntax because GL and RTL simulations are done using iVerilog, while GL+SDF simulations are done using CVC. The tools use different syntax for including files.

[proppy]

@marwaneltoukhy is https://github.com/efabless/caravel_user_project/blob/main/verilog/rtl/uprj_netlists.v also used in simulation?

[marwaneltoukhy]

@proppy No it's not, at least not the default flow. Investigating if some users might be using it for any other reason, I don't want to remove a file that might end up breaking someone's flow.