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efabless / caravel_user_project

https://caravel-user-project.readthedocs.io
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DRVs in sram_1rw1r_32_256_8_sky130 #178

Open m-usama-z opened 2 years ago

m-usama-z commented 2 years ago

The precheck is detecting lots of DRVs when using the SRAM cell sram_1rw1r_32_256_8_sky130. Is this SRAM cell not mentioned as an exception to DRC, like the other SRAM cells?

RTimothyEdwards commented 2 years ago

It is an old version of the SRAM cell and has been replaced by sky130_sram_1kbyte_1rw1r_32x256_8. I think the replacement is the same size, but I can't say without looking into it in detail.

m-usama-z commented 2 years ago

Ok. I was trying to use it only because it's the only SRAM for which I found timing libraries at multiple corners, to be more cautious against hold time violations.

On Thu, 3 Nov 2022, 22:46 R. Timothy Edwards, @.***> wrote:

It is an old version of the SRAM cell and has been replaced by sky130_sram_1kbyte_1rw1r_32x256_8. I think the replacement is the same size, but I can't say without looking into it in detail.

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