Full-chip STA (`make caravel-sta`) fails due to changed decap_12 cell references

[amm-efabless]

With tag 2024.09.12-1 (which incidentally, at the time of writing, is the same commit as the more-recent 2024.09.13-1), you will get this error if you try to run full-chip STA (i.e. the final make caravel-sta step):

Error: /home/.../caravel_user_project/caravel/verilog/gl/housekeeping_alt.v line 142360, syntax error, unexpected '[', expecting '('

This occurs since commit https://github.com/efabless/caravel-lite/commit/25a2260d385eab795823949628fd42f8b9287a1b where individual decap_12 cell instances were removed, and Verilog "arrayed instances" were used instead, and thus this sort of pattern was replaced:

...
 sky130_ef_sc_hd__decap_12 FILLER_100_159 (.VGND(VGND),
    .VNB(VGND),
    .VPB(VPWR),
    .VPWR(VPWR));
 sky130_ef_sc_hd__decap_12 FILLER_100_171 (.VGND(VGND),
    .VNB(VGND),
    .VPB(VPWR),
    .VPWR(VPWR));
 sky130_ef_sc_hd__decap_12 FILLER_100_183 (.VGND(VGND),
    .VNB(VGND),
    .VPB(VPWR),
    .VPWR(VPWR));
...

...and this sort of pattern is what took its place:

  sky130_ef_sc_hd__decap_12 decap_12[2308:0] (.VGND(VGND),
    .VNB(VGND),
    .VPB(VPWR),
    .VPWR(VPWR));

Note the [2308:0]. While this is valid Verilog, the tools (which?) don't support it in this format.

There are a few caravel & caravel-lite files that are affected by this.

I was able to work around this (for the time being) by just using an older tag when doing make setup for my caravel_user_project, i.e.:

MPW_TAG=mpw-9k make setup

[amm-efabless]

Steps I took to recreate this issue:

# Start clean:
unset OPENLANE_IMAGE_NAME OPENLANE_RUN_TAG OPENLANE_ROOT OPENLANE_TAG PDK_ROOT PDK MCW_ROOT

# Clone repo and check tag:
git clone --depth=1 https://github.com/efabless/caravel_user_project CUP-decap-test
cd CUP-decap-test
egrep 'MPW_TAG.*2024' Makefile
# => MPW_TAG ?= 2024.09.12-1
git log
# => 5020a223187c1693d5e5dd121e65ab7f6b770620, tags: 2024.09.13-1 and 2024.09.12-1

# Set everything up, and check tags:
make setup
cd caravel; git log; cd ..
# => a317f6d94d117702034babd0f6900395adbce85f, tags: 2024.09.13-1 and 2024.09.12-1
cd mgmt_core_wrapper; git log; cd ..
# => 503eda0790085712ffef7f4ad8934c7daed3237f, tags: mpw-9k/j/i/h, 2024.09.13-1, 2024.09.12-1, 2024.09.03-1
cd dependencies/openlane_src; git log; cd -
# => 30ee1388932eb55a89ad84ee43997bfe3a386421, tag: 2023.07.19-1
cd dependencies/timing-scripts; git log -1; cd -
# => 5b5dab63a257849dbb31881bec6f45439b6bdecb from 2023-10-19. MANY tags, including 2024.09.13-1, 2024.09.12-1

I then included these lines in the openlane/*/config.json files to speed up hardening, but also to use the different decap/fill strategy expected for CI2411+ (increasing GDS from 50MB to 120MB):

    "RUN_KLAYOUT_DRC": 0,
    "RUN_KLAYOUT_XOR": 0,
    "RUN_MAGIC_DRC": 0,
    "ROUTING_CORES": 16,
    "DECAP_CELL": "sky130_fd_sc_hd__decap_3",
    "FILL_CELL": "sky130_fd_sc_hd__fill_2 sky130_fd_sc_hd__fill_1",

I also edited verilog/rtl/user_defines.v to replace all "_INVALID" entries with GPIO_MODE_USER_STD_OUTPUT.

Next...

# Do hardens:
make user_proj_example
make user_project_wrapper

# Run full-chip STA steps:
make extract-parasitics
make create-spef-mapping
make caravel-sta

The last make caravel-sta is where it fails with:

exec> read_verilog /home/anton/WORK/dev/CUP-decap-test/caravel/verilog/gl/housekeeping_alt.v
exec> read_verilog /home/anton/WORK/dev/CUP-decap-test/caravel/verilog/gl/constant_block.v
exec> read_verilog /home/anton/WORK/dev/CUP-decap-test/caravel/verilog/gl/housekeeping_alt.v
Error: /home/anton/WORK/dev/CUP-decap-test/caravel/verilog/gl/housekeeping_alt.v line 142360, syntax error, unexpected '[', expecting '('
Error: /home/anton/WORK/dev/CUP-decap-test/caravel/verilog/gl/housekeeping_alt.v line 142360, syntax error, unexpected '[', expecting '('
Error: /home/anton/WORK/dev/CUP-decap-test/caravel/verilog/gl/housekeeping_alt.v line 142360, syntax error, unexpected '[', expecting '('
make[1]: *** [/home/anton/WORK/dev/CUP-decap-test/dependencies/timing-scripts/timing.mk:244: caravel-timing-typ-min] Error 1
make[1]: *** Waiting for unfinished jobs....
make[1]: *** [/home/anton/WORK/dev/CUP-decap-test/dependencies/timing-scripts/timing.mk:244: caravel-timing-typ-nom] Error 1
make[1]: *** [/home/anton/WORK/dev/CUP-decap-test/dependencies/timing-scripts/timing.mk:244: caravel-timing-typ-max] Error 1
make[1]: Leaving directory '/home/anton/WORK/dev/CUP-decap-test/dependencies/timing-scripts'
make: *** [Makefile:426: caravel-sta] Error 2

In this case, the file affected is https://github.com/efabless/caravel-lite/blob/main/verilog/gl/housekeeping_alt.v, but there are others that will come up.

[amm-efabless]

I did the following to work on a fix for this...

TL;DR: I did the following:

1. Forked caravel
2. Deleted 'caravel' dir from my caravel_user_project-based repo
3. Cloned my fork in as the replacement 'caravel' subdirectory
4. In caravel/verilog/gl, replaced all array instances of decap_12, fill_4, and fill_8 with expansions into individual cell instances instead, in each of these 4 files:
   • housekeeping_alt.v
   • housekeeping.v
   • caravan_core.v
   • caravel_core.v

Detailed description of what I did...

I forked https://github.com/efabless/caravel as https://github.com/amm-efabless/caravel -- NOTE: caravel-lite is generated from caravel, so I decided to go for the source.

I then went into my CUP-decap-test clone of caravel_user_project (as seen above)...

# Throw away old caravel-lite:
rm -rf caravel
# Clone my fork of the full caravel into CUP-decap-test, instead (warning: 17 GB):
git clone git@github.com:amm-efabless/caravel.git caravel
# Try running again to verify full-chip STA still breaks in the same way:
make caravel-sta

Now find any GL files that are using array instances by doing cd caravel; egrep -r --include="*.v" -i '[a-z0-9_]+\[[0-9]+:0\]\s*\(' verilog/gl/ -- Output is:

verilog/gl/housekeeping_alt.v:  sky130_ef_sc_hd__decap_12 decap_12[2308:0] (.VGND(VGND),
verilog/gl/housekeeping_alt.v:  sky130_ef_sc_hd__fill_4 fill4[768:0] (.VGND(VGND),
verilog/gl/housekeeping_alt.v:  sky130_ef_sc_hd__fill_8 fill8[768:0] (.VGND(VGND),
verilog/gl/housekeeping.v:  sky130_ef_sc_hd__decap_12 decap_12[1815:0] (.VGND(VGND),
verilog/gl/housekeeping.v:  sky130_ef_sc_hd__fill_4 fill4[604:0] (.VGND(VGND),
verilog/gl/housekeeping.v:  sky130_ef_sc_hd__fill_8 fill8[604:0] (.VGND(VGND),
verilog/gl/caravan_core.v: sky130_ef_sc_hd__decap_12 EF_decap_12[53703:0] (.VGND(vssd),
verilog/gl/caravan_core.v: sky130_ef_sc_hd__fill_4 EF_fill_4[53702:0] (.VGND(vssd),
verilog/gl/caravan_core.v: sky130_ef_sc_hd__fill_8 EF_fill_8[53702:0] (.VGND(vssd),
verilog/gl/caravel_core.v: sky130_ef_sc_hd__decap_12 EF_decap_12[65364:0] (.VGND(vssd),
verilog/gl/caravel_core.v: sky130_ef_sc_hd__fill_4 EF_fill_4[57192:0] (.VGND(vssd),
verilog/gl/caravel_core.v: sky130_ef_sc_hd__fill_8 EF_fill_8[57192:0] (.VGND(vssd),

Across the 4 files, we see:

• The pattern is always 3 types of devices, in order: decap_12, fill4, and fill8 -- sometimes though with slightly different names for the instances (not that I think it matters).
• decap_12 is always one quantity (e.g. 2308), while the next 2 are always an equal quantity (e.g. 768).
• The power and ground net names differ between files.
• From inspection, I've found that these always appear at the end of each file.

For each of the 4 files in turn:

• I took note of their power/ground net names, and the 3 max indices of array indices.
• I deleted the tail end of each file, i.e. the first decap_12 array instance, all the way to the end of the file, including deleting the final endmodule
• I used the clunky script below (called recap.sh) to generate and append replacement elaborated (individual) instances for all the cells on each file...

#!/bin/bash
gnd="${gnd:-VGND}" # Default to VGND
pwr="${pwr:-VPWR}" # Default to VPWR
for i in $(seq -f "%06g" 0 $1); do
cat <<EOH
  sky130_ef_sc_hd__decap_12 EF_decap12_$i (.VGND($gnd),
    .VNB($gnd),
    .VPB($pwr),
    .VPWR($pwr));
EOH
done
for i in $(seq -f "%06g" 0 $2); do
cat <<EOH
  sky130_ef_sc_hd__fill_4 EF_fill4_$i (.VGND($gnd),
    .VNB($gnd),
    .VPB($pwr),
    .VPWR($pwr));
EOH
done
for i in $(seq -f "%06g" 0 $3); do
cat <<EOH
  sky130_ef_sc_hd__fill_8 EF_fill8_$i (.VGND($gnd),
    .VNB($gnd),
    .VPB($pwr),
    .VPWR($pwr));
EOH
done
echo "endmodule"

In particular, I ran:

pwr=VPWR gnd=VGND ./recap.sh 2308 768 768 >> verilog/gl/housekeeping_alt.v
pwr=VPWR gnd=VGND ./recap.sh 1815 604 604 >> verilog/gl/housekeeping.v
pwr=vccd gnd=vssd ./recap.sh 53703 53702 53702 >> verilog/gl/caravan_core.v
pwr=vccd gnd=vssd ./recap.sh 65364 57192 57192 >> verilog/gl/caravel_core.v

I then manually checked each file to make sure they seemed valid.

I went back up a directory level into my CUP-decap-test repo and ran make caravel-sta again.

There are no errors now, and the full-chip STA results are as expected.

I committed the changes in 'caravel' and pushed to my fork: https://github.com/amm-efabless/caravel/commit/324aa7a44327be13e883667d002c8e90ed755367