There are several things that are incorrect in openlane/SRAM_1024x32/config.json because they are using variables that only work in OL2, hence the harden doesn't have the intended result, namely:
Power nets don't get connected?
Routing obstructions are not respected?
I think these are the ones that are wrong, and what they should be changed to:
VERILOG_POWER_DEFINE should be SYNTH_USE_PG_PINS_DEFINEShowever I tried running the flow with this change, and it fails with: ERROR: Module `EFSRAM_1024x32_wrapper' referenced in module `SRAM_1024x32' in cell `SRAM_0' does not have a port named 'vpwrp'. -- Without being able to use this, I don't think power nets get connected. Without SYNTH_USE_PG_PINS_DEFINES we instead see: [ERROR]: Can't find vpwrm and vgnd domain. Make sure that both exist in VPWR and VGND. (though the flow still completes).
There are several things that are incorrect in
openlane/SRAM_1024x32/config.json
because they are using variables that only work in OL2, hence the harden doesn't have the intended result, namely:I think these are the ones that are wrong, and what they should be changed to:
VERILOG_POWER_DEFINE
should beSYNTH_USE_PG_PINS_DEFINES
however I tried running the flow with this change, and it fails with:ERROR: Module `EFSRAM_1024x32_wrapper' referenced in module `SRAM_1024x32' in cell `SRAM_0' does not have a port named 'vpwrp'.
-- Without being able to use this, I don't think power nets get connected. WithoutSYNTH_USE_PG_PINS_DEFINES
we instead see:[ERROR]: Can't find vpwrm and vgnd domain. Make sure that both exist in VPWR and VGND.
(though the flow still completes).ROUTING_OBSTRUCTIONS
should beGRT_OBS
PDN_MACRO_CONNECTIONS
should beFP_PDN_MACRO_HOOKS
VERILOG_DEFINES
should beSYNTH_DEFINES
PL_TARGET_DENSITY_PCT
should bePL_TARGET_DENSITY
and expressed in 0..1 range.RUN_ANTENNA_REPAIR
should beGRT_REPAIR_ANTENNAS
QUIT_ON_PDN_VIOLATIONS
RUN_POST_GRT_RESIZER_TIMING
RUN_POST_GRT_DESIGN_REPAIR