efabless / clear

Apache License 2.0
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"synth_top.tcl" is missing #15

Closed msaideroglu closed 2 years ago

msaideroglu commented 2 years ago

The script "synth_top.tcl" file in config.tcl in main branch is missing. Config.tcl in older branches also give this errors:

[STEP 3] [INFO]: Running Initial Floorplanning... [ERROR]: during executing openroad script /openlane/scripts/openroad/floorplan.tcl [ERROR]: Exit code: 1 [ERROR]: full log: ../home/msaid/ClearFPGA_Workspace/clear/openlane/fpga_core/runs/22_08_22_16_17/logs/floorplan/3-initial_fp.log [ERROR]: Last 10 lines: set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINITY) [get_clocks $::env(CLOCK_PORT)] puts "\[INFO\]: Setting clock transition to: $::env(SYNTH_CLOCK_TRANSITION)" [INFO]: Setting clock transition to: 0.15 set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks $::env(CLOCK_PORT)] puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %" [INFO]: Setting timing derate to: 0.5 % set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}] set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}] Error: floorplan.tcl, 93 can't read "::env(DIE_AREA)": no such variable child process exited abnormally