Cocotb updates

[M0stafaRady]

• Adding initial cocotb tests for testing the chain and and gate design
• Adding power connection to the fpga RTL

[marwaneltoukhy]

Why aren't we running verification on the gl netlist post synthesis? This netlist should have the power ports.

[M0stafaRady]

@marwaneltoukhy What do you mean by not running verification post synthesis ?

[marwaneltoukhy]

why aren't you running the verification on the gl netlist coming out of OpenLane?

[M0stafaRady]

We do

[marwaneltoukhy]

Then why are you editing these files? The gl netlist coming out of OpenLane is already powered.

[M0stafaRady]

This is for the RTL files which contain sky130 cells

[marwaneltoukhy]

These aren't RTL files, these are netlists as well. That's why I am asking why aren't you just using the ones coming out of OpenLane.

[M0stafaRady]

These are readable netlist so it's easier to debug them compared with what Openlane provided.

[marwaneltoukhy]

Okay, just make sure that nothing else changed. I'm just worried that we mess with source code, and something might change without us knowing.

These are readable netlist so it's easier to debug them compared with what Openlane provided.

[M0stafaRady]

I checked these changes more than one time but I will really appreciate if someone else also have a look to make sure the script have not corrupted anything.