How to syntesize and place & route for CLEAR ?

efabless / clear

Apache License 2.0

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Open Martoni opened 9 months ago

Martoni commented 9 months ago

Hello,

Is there a tutorial to explain step by step how to synthesize a design and place & route for CLEAR eFPGA ?

And also, is there static timing analyser software that targeting CLEAR ?

Thanks.

chaseadam commented 5 months ago

just received mine yesterday and am hoping for a step by step for some of the examples.