Proposing DRC performance patches for #17

[klayoutmatthias]

Fixes #17

I'm trying once again to propose some fundamental changes to improve performance in deep mode ;)

Specifically:

• An alternative implementation of the LDMOS checks
• Skip merging of input layers in deep mode
• Some minor patches - e.g. turning metal.enclosing(via, ...) into via.enclosed(metal, ...).

With these changes, the test case from #17 executes in 2700s (4 threads, deep mode, no connectivity checks) at around 3.5G peak memory. Some DRC issues are flagged which IMHO are real issues. Specifically, V4.4a fails which is because the layout is not made for 5LM (metal5 is on layer 81 which it should be on 53 for top metal). I don't see how to enable 6LM (option D?), so V4.4a is rightfully complaining about missing top metal for via4.

It's up to you whether to accept this patch or not. But to state that clearly: without optimization - specifically the ones proposed here - a reasonable DRC runtime cannot be achieved. Flat mode rules out for this complexity, deep mode can be very fast but also very slow without optimization. There is no "magic KLayout patch" that makes an any DRC deck run fast. There are surely some problems that can be mitigated on KLayout side, but there is no universal coding scheme for complex DRC rules and every tool works differently. So you need to be willing to optimize for a specific tool. For some more details see my comments on #17.

• [ ] Tests pass
• [ ] Appropriate changes to README are included in PR

[atorkmabrains]

@klayoutmatthias I have taken all your updates here: https://github.com/mabrains/globalfoundries-pdk-libs-gf180mcu_fd_pr

I think it's better to open PR on mabrains version as that's where I do all the development.

[klayoutmatthias]

Thanks, I will do so in the future.

Matthias