Closed StanleyAlwaysLoveYou closed 1 year ago
@StanleyAlwaysLoveYou Could you please upload your testcase ?
and what is the run command you have used ?
Please use this PV repo for DRC/LVS
@StanleyAlwaysLoveYou I'll close this issue as it has been addressed. Please let me know if you need more help.
Expected Behavior
When I ran the LVS on the layout consists of a resistor and a capacitor, the LVS should indicate that there are a resistor and a capacitor in the layout.
Actual Behavior
LVS only recognize the resistor but the MIM cap in the layout.
Specifications