Open c-93 opened 1 month ago
As you've surmised, the script looks for a power pin but does not find it. What this likely means is that the LEF view of the design states one thing about the power pins and the Verilog view (from which the JSON hierarchy of the design is created) states another thing.
I'll try to make the error messages a bit better.
In the meantime, could you please verify the top-level pins are identical?
Description
While instantiating macros,
Odb.SetPowerConnections
in OpenLane2 sometimes fails for some macros.Based on the logs: Do you have an idea what is happening?
I think the algorithm searches for a power pin, but doesn't find it. Or it iterates over pins, which are somehow not included.
How can this be debugged from within the container?
Expected Behavior
Don't fail.
Environment report
Reproduction material
Unfortunately, I cannot provide the project for reproduction. I hope the logs provide enough information.
Relevant log output