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efabless / openlane2

The next generation of OpenLane, rewritten from scratch with a modular architecture
https://openlane2.readthedocs.io/
Apache License 2.0
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Rename top level after application of parameters early enough. Fixes DFFRAM with OpenLane2.0.8 #491

Open donnie-j opened 1 week ago

donnie-j commented 1 week ago

Moves the rename of top module to before selecting it. This fixes a problem with mainline OpenLane2 and e.g. DFFRAM where needed modules are optimised away and then synthesis fails:

...
5.23. Analyzing design hierarchy..
Top module:  $paramod\RAM128\WSIZE=32'00000000000000000000000000000100
...
Removed 30 unused modules.
ERROR: No such module: RAM128

I believe this was introduced around 2.0.0b17, during the refactoring of the synthesis script.

It needs to be run on a multiple designs to prove that the new ordering doesn't negatively affect something unexpected.

donn commented 1 week ago

Yosys is super chaotic, so let's hope the metrics don't catch fire across the board 😅

donnie-j commented 1 week ago

Yosys is super chaotic, so let's hope the metrics don't catch fire across the board 😅

Indeed. I believe this does nothing to the topology... I hope all it does is rename the top cell correctly if needed, and is otherwise a no op.

I just ran a fairly large J-Core J2 CPU+FPU macro (almost .8mm^2 in sky130 hd cells) we've been using as a test, and got a byte for byte identical verilog netlist out of the synthesis step before and after this change... so that is encouraging. Yosys 0.41, and GHDL 4.1.0 though, which is not the typical use case.