When using Verilog typically propagation delays are modeled for correct timing in the simulations. For example:
always @(posedge clk or negedge rst_n)
begin
if(!rst_n) begin
d<= #1 'b0;
d2<= #1 'b0;
end
else begin
d2<= #1 in; // in-> d2 -> d=out
d <= #1 d2;
end
end
As you can see the inertial delay is modeled and is pretty much a standard technique for system simulations.
When running openlane, the Linter bails out stating this is an error. The current workaround is to add a directive into the code (which stops code portability). Eg this pragma is added to the code at the beginning:
/*verilator timing_off*/
This solves the issue but is an ugly fix.
Proposal
I suggest there be a way of passing command-line arguments to all of the tools. In this example the config.json line would be:
"LINTER_CMD_LINE_ARGS": " --no-timing"
A set of xxxx_CMD_LINE_ARGS could be added to all the tools and this would provide maximum flexibility. For instance one may like to add placement arguments to OpenROAD, etc. This would be a great way of doing this.
Description
When using Verilog typically propagation delays are modeled for correct timing in the simulations. For example:
As you can see the inertial delay is modeled and is pretty much a standard technique for system simulations.
When running openlane, the Linter bails out stating this is an error. The current workaround is to add a directive into the code (which stops code portability). Eg this pragma is added to the code at the beginning:
This solves the issue but is an ugly fix.
Proposal
I suggest there be a way of passing command-line arguments to all of the tools. In this example the config.json line would be:
"LINTER_CMD_LINE_ARGS": " --no-timing"
A set of xxxx_CMD_LINE_ARGS could be added to all the tools and this would provide maximum flexibility. For instance one may like to add placement arguments to OpenROAD, etc. This would be a great way of doing this.