Is the Raven SPI functionnal ?

[sofchet]

Hi,

I was wondering whether the Raven_SPI was tested ? and in case it is not needed, what would be the safe way to get rid of the Raven_SPI without hurting the design ?

Thanks,

[RTimothyEdwards]

The SPI in the Raven chip is considered a "housekeeping" SPI. It was designed largely to keep a number of critical functions away from the processor itself and allow for more convenient testing. Mostly this was deemed necessary because Raven was a first-of-its-kind proof of concept. In case anything was wrong with the design, I wanted multiple ways to access the chip and see what was going on. As it turned out, the Raven chip worked perfectly well. So, the short answer is that there is nothing mandatory about the housekeeping SPI. If you remove it, just make sure that the critical components it touches (like the PLL, the crystal oscillator, voltage references, etc.) are hard-wired to the right values (i.e., enabled), or memory-mapped into the processor area, with the correct defaults. If you memory-map any of those signals, watch for the ones that will self-destruct; e.g., turning off the voltage regulator will instantly kill the processor.

If you are looking at the RTL for the Ravenna design on efabless.com, note that the housekeeping SPI there has an additional useful function called "pass-through" mode, which allows the housekeeping SPI to be used to access the SPI flash chip. That allows the SPI flash chip to be connected solely to the processor, without the need to jumper between the processor and the FTDI chip when switching between flash programming and application run-time.

Another option I have considered but never implemented is to keep the housekeeping SPI, but let the SPI signals be shared with GPIO. Any program would then be able to disable the SPI communication and make use of the GPIO pins for other purposes.

Regards, Tim

[sofchet]

Oh okay I see, thanks for the detailed and clear answer !