Closed antonblanchard closed 2 years ago
The SRAM behaviourals are overly chatty. Microwatt does not need the caravel management engine core, so holds it in reset. Even so, the CI tests are seeing tens of thousands of the following:
575306 Reading simplebus_minimal_tb.uut.soc.core.sky130_sram_2kbyte_1rw1r_32x512_8 addr0=000000000 dout0=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Set VERBOSE = 0, which someone can override if they want to see every read and write from the SRAM.
See #12
mguthaus
commented
2 years ago
The SRAM behaviourals are overly chatty. Microwatt does not need the caravel management engine core, so holds it in reset. Even so, the CI tests are seeing tens of thousands of the following:
575306 Reading simplebus_minimal_tb.uut.soc.core.sky130_sram_2kbyte_1rw1r_32x512_8 addr0=000000000 dout0=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Set VERBOSE = 0, which someone can override if they want to see every read and write from the SRAM.