Liberty Files - Githubissues

nayiri-k commented 3 years ago

Hello,

I have been using these pre-compiled SRAM macros for a recent tapeout in Sky130. We found that the endian-ness of the liberty files is ambiguous, see the example file snippets below for the addr port; while the first part defines addr[0:7], the second part has addr[7:0].

  type (addr){
    base_type : array;
    data_type : bit;
    bit_width : 8;
    bit_from : 0;
    bit_to : 7;
    }  
......

pin(addr0[7:0]){

This error caused bit-reversed connections in synthesis (e.g. signal addr0[7] connected to SRAM port addr0[0]). For reference, we used Cadence Genus/Innovus in the VLSI flow.

The only change we made that completely fixed this issue (giving us an LVS-clean design) was reversing the bit_from and bit_to values in the liberty files, see below.

  type (addr){
    base_type : array;
    data_type : bit;
    bit_width : 8;
    bit_from : 7;
    bit_to : 0;
    }

Let me know if this is a change you plan to make, I currently have our VLSI flow manually hack this reversal so I would need to know to remove the hack.

Thanks, Nayiri

mguthaus commented 3 years ago

Thank you for pointing this out. It does look like an error. I will double check and make a patch soon.

mguthaus commented 3 years ago

I pushed a hand fix to the sky130_sram_macros in main and dev. I also made a fix to OpenRAM for future results.

efabless / sky130_sram_macros_old

Liberty Files #7