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efabless / sky130_sram_macros_old

Apache License 2.0
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Verilog syntax error? #8

Closed nayiri-k closed 3 years ago

nayiri-k commented 3 years ago

I'm trying to use the verilog files, but I encounter an error during RTL simulation. It seems the mem variable is used before it is declared (via this declaration: reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];). Moving this declaration before mem is referenced resolved the error in my simulation.

mguthaus commented 3 years ago

Which simulator?

Bugs should be reported on the OpenRAM github: https://github.com/VLSIDA/OpenRAM

nayiri-k commented 3 years ago

Simulating with Synopsys VCS. But the issue is referencing a variable before declaring it, which should just never be done. I'll move this issue to the OpenRAM github, thanks!

mguthaus commented 3 years ago

Thanks. It's interesting that the open source simulators don't complain about this...