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efeslab / hardware-bugbase

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Add a shared "synth" make target to synthesize instrumented HARP-based applications #2

Closed Alkaid-Benetnash closed 3 years ago

Alkaid-Benetnash commented 3 years ago
  1. make synth will call sv2v.py to instrument verilog code.
  2. make synth -j can run multiple synthesize job at the same time.