Add SystemVerilog formatting capability

jecassis commented 3 years ago

Add the option to use a formatter such as Verible

eirikpre commented 3 years ago

Excellent, I've been tracking Verible for a while. I think this will be one of the major platforms going forward. I was ready to investigate Verible for parsing/linting, but no macro support made me hold back for the moment.

jecassis commented 3 years ago

Verible is getting there but still needs some work. Particularly for parsing.

For linting I didn't want to integrate it like the other tools since you suggested in some issues using a task instead due to the maintenance burden. At the moment using it more as a sanity check before starting a build.

Verible does not like some very peculiar code such as the following (with drive strength):

wire (supply1, highz0) supply_vdd = vdd_en ? 1'b1: 1'bz;
wire (supply0, highz1) supply_vss = vss_en ? 1'b0: 1'bz;

And handles these types of declarations poorly (with the comma before combined with compiler directives):

`ifdef LEGACY
  , input sin
`else
  , input [3:0] sin
`endif
  , output [3:0] sout

The equivalent tests also fail in sv-tests so I assume they know about it.

eirikpre / VSCode-SystemVerilog

Add SystemVerilog formatting capability #105