eirikpre / VSCode-SystemVerilog

SystemVerilog support in VS Code
MIT License
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Feature Request: Show verilog input/output/inout using different symbol then instance #116

Closed GalTabov closed 2 years ago

GalTabov commented 3 years ago

Currently both IO of Verilog modules (input/output/inout) and Verilog instances shown in Outline as SymbolKind.Field. This makes difficult to distinguish them when navigating in design: image

Proposal is to show IO's as SymbolKind.Boolean or maybe other unused symbol. This can be achived by adding code case"input":case"output":case"inout":return r.SymbolKind.Boolean; before case"module":default:return r.SymbolKind.Field in /.vscode/extensions/eirikpre.systemverilog-0.11.3/dist/client/extension.js file. With this modification Outline window will be like this: image Moreover because IO are different symbol class, they can be switched off in Outline settings.

Personally I do this modification for quite long time locally, but unfortunatelly I have to do it after each extension update and that takes time. Maybe if this modification looks usefull for others it can be added to extension?

joecrop commented 2 years ago

Hi @GalTabov, I have made the modification, but unfortunately it only works for ports that aren't typed and written outside of the declaration line. The ports that have types (i.e. wire, logic, etc.) are typed as such and not typed as input/output. But, this is a step in the right direction, I suppose...

image