Go to definition doesn't work for "spi" module name

[hi0t]

OS: Ubuntu 22.04 (WSL) Vscode: 1.89.1 SystemVerilog: 0.13.9

1. Create an empty project with two modules:

   
   module top (
   input clk
   );

spi spi(clk);

endmodule

```systemverilog
module spi(
    input clk
);

endmodule

2. Click the index button
3. Try to go to the spi module from the top module and nothing happens.

If you rename the spi module, for example, to xyz, then "Go to definition" starts to work. What is this magical name "spi"?

[calint]

The problem seems to be when the module instance has same name as the module. Having the same issue.