Closed AitBits closed 5 years ago
Oh noes :(
I'll look into it soon
That commit just looks like a version bump to me, and the problem persists on my side. I think you forgot to stage some file?
Ah yes, I made a typo in the commit message, so I linked the wrong issue. Here is the commit: 62c235c0846e2db17fb000dd7385a859ec052136
That fixed it on my part, the output is piped to Output/System Verilog Language Server when the server logs.
Yeah, that seems got fixed but I'm getting another problem. I will open a separate issue.
When I tried to compile a file through the command palette or compile on save option, it does nothing and returns no output.
Downgrading to 0.8.4 fixes the issue.