search

eirikpre / VSCode-SystemVerilog

SystemVerilog support in VS Code
MIT License
128 stars 50 forks source link

Use SureLog for ANTLR based parser? #77

Open mithro opened 4 years ago

mithro commented 4 years ago

https://github.com/alainmarcel/Surelog

This project aims at providing a complete System Verilog 2017 front-end: a preprocessor, a parser, an elaborator for both design and testbench.

The preprocessor and the parser use Antlr 4.72 as a parser generator. The preprocessor and the parser ASTs are made persistent on disk using Google Flatbuffers, enabling incremental compilation. The tool is built thread safe and performs multithread parsing. Large files/modules/packages are splitted for multi-threading compilation. Surelog accepts IEEE Simulator-compliant project specification. Surelog issues Errors/Warning/Info/Notes about language compliance. Surelog allows for pre-compiled packages (UVM,...). A comprehensive Python API allows to: listen or visit the Parser grammar and create custom linting rules Visit the design data model and create custom linting rules Customize the message formats Waive messages

SureLog does very well on sv-tests (https://symbiflow.github.io/sv-tests/).

Otherwise you could try to collaborate on the ANTLR grammar?

mithro commented 4 years ago

https://github.com/eirikpre/VSCode-SystemVerilog/tree/master/src/compiling/ANTLR/grammar vs https://github.com/alainmarcel/Surelog/tree/master/grammar