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ejk43 / rfnoc-neuralnet

RFNoC OOT module for FPGA-based neural network implementation
GNU General Public License v3.0
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Problems with synthesis #1

Open frestuc opened 6 years ago

frestuc commented 6 years ago

Tried to execute code (the one in the Xilinx repository) with newest version of RFNOC after having applied your patch to uhd-fpga. However the design does not synthesize.

I believe that the changes you applied to uhd-fpga clash with the newest version of RFNOC that uses Vivado 2017.4.

This is what I'm seeing:

frestuc@frestuc-ubuntu:~/Documents/rfnoc/src/uhd-fpga/usrp3/tools/scripts$ ./uhd_image_builder.py ex1layer fft window -t X310_RFNOC_HLS_HG -d X310
--Using the following blocks to generate image:
    * ex1layer
    * fft
    * window
Adding CE instantiation file for 'X310_RFNOC_HLS_HG'
changing temporarily working directory to /home/frestuc/Documents/rfnoc/src/uhd-fpga/usrp3/tools/scripts/../../top/x300
Setting up a 64-bit FPGA build environment for the USRP-X3x0...
- Vivado: Found (/opt/Xilinx/Vivado/2015.4/bin)
- Vivado HLS: Found (/opt/Xilinx/Vivado_HLS/2015.4/bin)

Environment successfully initialized.
make -f Makefile.x300.inc hls NAME=X310_RFNOC_HLS_HG ARCH=kintex7 PART_ID=xc7k410t/ffg900/-2 BUILD_1G=1 BUILD_10G=1 SFP0_1GBE=1 SFP1_10GBE=1  RFNOC=1 X310=1 HLS=1 EXTRA_DEFS="BUILD_1G=1 BUILD_10G=1 SFP0_1GBE=1 SFP1_10GBE=1  RFNOC=1 X310=1 HLS=1"
make[1]: Entering directory '/home/frestuc/Documents/rfnoc/src/uhd-fpga/usrp3/top/x300'
BUILDER: Checking tools...
* GNU bash, version 4.3.48(1)-release (x86_64-pc-linux-gnu)
* Python 2.7.12
* Vivado v2015.4 (64-bit)
========================================================
BUILDER: Building HLS IP addsub_hls
========================================================
BUILDER: Staging HLS IP in build directory...
BUILDER: Reserving IP location: /home/frestuc/Documents/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/addsub_hls
BUILDER: Building HLS IP...
================================================================
  Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
  Version 2015.4
  Build 1412921 on Wed Nov 18 09:58:55 AM 2015
  Copyright (C) 2015 Xilinx Inc. All rights reserved.
================================================================
@I [HLS-10] Running '/opt/Xilinx/Vivado_HLS/2015.4/bin/unwrapped/lnx64.o/vivado_hls'
            for user 'frestuc' on host 'frestuc-ubuntu' (Linux_x86_64 version 4.13.0-38-generic) on Wed Apr 11 08:26:53 EDT 2018
            in directory '/home/frestuc/Documents/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2'
@I [HLS-10] Creating and opening project '/home/frestuc/Documents/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/addsub_hls'.
@I [HLS-10] Creating and opening solution '/home/frestuc/Documents/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/addsub_hls/solution'.
@I [HLS-10] Setting target device to 'xc7k410tffg900-2'
BUILDER: Using include location : 
BUILDER: Adding C/C++ : /home/frestuc/Documents/rfnoc/src/uhd-fpga/usrp3/lib/hls/addsub_hls/addsub_hls.cpp
@I [HLS-10] Adding design file '/home/frestuc/Documents/rfnoc/src/uhd-fpga/usrp3/lib/hls/addsub_hls/addsub_hls.cpp' to the project
BUILDER: Executing tcl script : /home/frestuc/Documents/rfnoc/src/uhd-fpga/usrp3/lib/hls/addsub_hls/addsub_hls.tcl
@I [SYN-201] Setting up clock 'default' with a period of 5ns.
@I [HLS-10] Analyzing design file '/home/frestuc/Documents/rfnoc/src/uhd-fpga/usrp3/lib/hls/addsub_hls/addsub_hls.cpp' ... 
@I [HLS-10] Validating synthesis directives ...
@I [HLS-10] Starting code transformations ...
@I [HLS-10] Checking synthesizability ...
@I [XFORM-1101] Packing variable 'sub.data' (/home/frestuc/Documents/rfnoc/src/uhd-fpga/usrp3/lib/hls/addsub_hls/addsub_hls.cpp:11) into a 32-bit variable.
@I [XFORM-1101] Packing variable 'add.data' (/home/frestuc/Documents/rfnoc/src/uhd-fpga/usrp3/lib/hls/addsub_hls/addsub_hls.cpp:11) into a 32-bit variable.
@I [XFORM-1101] Packing variable 'a.data' (/home/frestuc/Documents/rfnoc/src/uhd-fpga/usrp3/lib/hls/addsub_hls/addsub_hls.cpp:11) into a 32-bit variable.
@I [XFORM-1101] Packing variable 'b.data' (/home/frestuc/Documents/rfnoc/src/uhd-fpga/usrp3/lib/hls/addsub_hls/addsub_hls.cpp:11) into a 32-bit variable.
@I [HLS-111] Elapsed time: 2.64649 seconds; current memory usage: 63.9 MB.
@I [HLS-10] Starting hardware synthesis ...
@I [HLS-10] Synthesizing 'addsub_hls' ...
@I [HLS-10] ----------------------------------------------------------------
@I [HLS-10] -- Scheduling module 'addsub_hls' 
@I [HLS-10] ----------------------------------------------------------------
@I [SCHED-11] Starting scheduling ...
@I [SCHED-11] Finished scheduling.
@I [HLS-111] Elapsed time: 0.011884 seconds; current memory usage: 64.1 MB.
@I [HLS-10] ----------------------------------------------------------------
@I [HLS-10] -- Exploring micro-architecture for module 'addsub_hls' 
@I [HLS-10] ----------------------------------------------------------------
@I [BIND-100] Starting micro-architecture generation ...
@I [BIND-101] Performing variable lifetime analysis.
@I [BIND-101] Exploring resource sharing.
@I [BIND-101] Binding ...
@I [BIND-100] Finished micro-architecture generation.
@I [HLS-111] Elapsed time: 0.00456 seconds; current memory usage: 64.2 MB.
@I [HLS-10] ----------------------------------------------------------------
@I [HLS-10] -- Generating RTL for module 'addsub_hls' 
@I [HLS-10] ----------------------------------------------------------------
@I [RTGEN-500] Setting interface mode on port 'addsub_hls/a_data' to 'axis'.
@I [RTGEN-500] Setting interface mode on port 'addsub_hls/a_last_V' to 'axis'.
@I [RTGEN-500] Setting interface mode on port 'addsub_hls/b_data' to 'axis'.
@I [RTGEN-500] Setting interface mode on port 'addsub_hls/b_last_V' to 'axis'.
@I [RTGEN-500] Setting interface mode on port 'addsub_hls/add_data' to 'axis'.
@I [RTGEN-500] Setting interface mode on port 'addsub_hls/add_last_V' to 'axis'.
@I [RTGEN-500] Setting interface mode on port 'addsub_hls/sub_data' to 'axis'.
@I [RTGEN-500] Setting interface mode on port 'addsub_hls/sub_last_V' to 'axis'.
@I [RTGEN-500] Setting interface mode on function 'addsub_hls' to 'ap_ctrl_none'.
@I [RTGEN-100] Finished creating RTL model for 'addsub_hls'.
@I [HLS-111] Elapsed time: 0.012248 seconds; current memory usage: 64.5 MB.
@I [HLS-10] Finished generating all RTL models.
@I [WSYSC-301] Generating RTL SystemC for 'addsub_hls'.
@I [WVHDL-304] Generating RTL VHDL for 'addsub_hls'.
@I [WVLOG-307] Generating RTL Verilog for 'addsub_hls'.
@I [IMPL-8] Exporting RTL as an IP in IP-XACT.

****** Vivado v2017.4 (64-bit)
  **** SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
  **** IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

source run_ippack.tcl -notrace
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2017.4/data/ip'.
INFO: [Common 17-206] Exiting Vivado at Wed Apr 11 08:27:20 2018...
@I [HLS-112] Total elapsed time: 53.200 seconds; peak memory usage: 64.5 MB.
BUILDER: Releasing IP location: /home/frestuc/Documents/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/addsub_hls
========================================================
BUILDER: Building IP ten_gig_eth_pcs_pma
========================================================
BUILDER: Staging IP in build directory...
BUILDER: Reserving IP location: /home/frestuc/Documents/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma
BUILDER: Retargeting IP to part kintex7/xc7k410t/ffg900/-2...
BUILDER: Building IP...

****** Vivado v2015.4 (64-bit)
  **** SW Build 1412921 on Wed Nov 18 09:44:32 MST 2015
  **** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
    ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.

source /home/frestuc/Documents/rfnoc/src/uhd-fpga/usrp3/tools/scripts/viv_generate_ip.tcl
# set xci_file         $::env(XCI_FILE)               ;
# set part_name        $::env(PART_NAME)              ;
# set gen_example_proj $::env(GEN_EXAMPLE)            ;
# set synth_ip         $::env(SYNTH_IP)               ;
# set ip_name [file rootname [file tail $xci_file]]   ;
# file delete -force "$xci_file.out"
# create_project -part $part_name -in_memory -ip
# set_property target_simulator XSim [current_project]
# add_files -norecurse -force $xci_file
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2015.4/data/ip'.
ERROR: [IP_Flow 19-395] Problem reading Component: see 'xilinx:parameterInfo' near line 0 in /home/frestuc/Documents/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xml: Bad end of element
CRITICAL WARNING: [IP_Flow 19-182] Failed to load BOM file '/home/frestuc/Documents/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xml'.
CRITICAL WARNING: [IP_Flow 19-183] Failed to load IP instance 'ten_gig_eth_pcs_pma'.
CRITICAL WARNING: [IP_Flow 19-1835] Failed to recreate IP instance 'ten_gig_eth_pcs_pma'. Error reading project file(s).
ERROR: [Common 17-39] 'add_files' failed due to earlier errors.

    while executing
"add_files -norecurse -force $xci_file"
    (file "/home/frestuc/Documents/rfnoc/src/uhd-fpga/usrp3/tools/scripts/viv_generate_ip.tcl" line 22)
INFO: [Common 17-206] Exiting Vivado at Wed Apr 11 08:27:55 2018...
BUILDER: Releasing IP location: /home/frestuc/Documents/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma
/home/frestuc/Documents/rfnoc/src/uhd-fpga/usrp3/top/x300/ip/ten_gig_eth_pcs_pma/Makefile.inc:41: recipe for target '/home/frestuc/Documents/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci.out' failed
make[1]: *** [/home/frestuc/Documents/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci.out] Error 1
make[1]: Leaving directory '/home/frestuc/Documents/rfnoc/src/uhd-fpga/usrp3/top/x300'
Makefile:109: recipe for target 'X310_RFNOC_HLS_HG' failed
make: *** [X310_RFNOC_HLS_HG] Error 2
ejk43 commented 6 years ago

Definitely, the repo associated with Xilinx is the way to go-- this was my original development repo. I dont think it's quite as updated. You could definitely be right, the patches might conflict with the current uhd-fpga HEAD (or even conflict with the uhd-fpga HEAD as of September-ish 2017)