Closed faxvs closed 9 months ago
pcileech_screamer_m2 The code pcileech_screemer_m2 encountered the same error during compilation in Vavido [DRC UTLZ-1] Resource utilization: RAMB18 and RAMB36/FIFO over-utilized in Top Level Design (This design requires more RAMB18 and RAMB36/FIFO cells than are available in the target device. This design requires 109 of such cell types but only 100 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.)
@ekknod pls help me
who can help me?
try again now, should be good
现在再试一次,应该很好
Thank you very much for your update that resolved this issue. Thank you again for your efforts
Can you tell me which one is 35T? I only see 75T and 100T
Your code encountered the following issues while compiling in Vavido The core of 35T cannot be compiled and encountered this error. The core of 75T and 100T can be compiled smoothly
[DRC UTLZ-1] Resource utilization: RAMB18 and RAMB36/FIFO over-utilized in Top Level Design (This design requires more RAMB18 and RAMB36/FIFO cells than are available in the target device. This design requires 109 of such cell types but only 100 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.)
im using 35T 。i want know How to solve this problem?