Fixed and improved MDR1986VE3.h + cleanup

[in4lio]

1. MDR1986VE3.h: some definitions have been imported from MDR1986VE1T.h
2. MDR1986VE3.h: fixed __MPU_PRESENT, __NVIC_PRIO_BITS, EBC_RAM_CYCLES_WS_HOLD_Msk
3. MDR1986VE3.h: replaced TABs
4. cleanup

[eldarkg]

Where is in doc?

#define TIMER_CNTRL_CNT_MODE_UP_DOWN_DIR_AUTO_EVENT_1   0x03

[eldarkg]

Where are this bits?

Таблица 269 – Описание бит регистра CNTRL
EVENT_SEL[3:0]:
4’b1001 – событие заднего фронта ETR
4’b1010 – CNT == ARR в таймере 4

[eldarkg]

Code:

#define RST_CLK_CLOCK_STATUS_HSE_ALL_RDY        ((uint32_t)0x0000000C)

it will be good to write:

#define RST_CLK_CLOCK_STATUS_HSE_ALL_RDY        (RST_CLK_CLOCK_STATUS_HSE_RDY |\
                                                 RST_CLK_CLOCK_STATUS_HSE_RDY2)

[eldarkg]

Define constants that defined yet: 1 2 3 This lines should be deleted.

[eldarkg]

In accordance:

Таблица 293 – Описание бит регистра ADC1_CFG
DelayGo[2:0]
000 – 0 тактов PCLK
001 – 1 такт PCLK
...
111 – 7 тактов PCLK

but you have defined range 1-8 clocks:

#define ADC1_CFG_DELAY_GO_1_CPU_CLK             0x00
#define ADC1_CFG_DELAY_GO_2_CPU_CLK             0x01
#define ADC1_CFG_DELAY_GO_3_CPU_CLK             0x02
#define ADC1_CFG_DELAY_GO_4_CPU_CLK             0x03
#define ADC1_CFG_DELAY_GO_5_CPU_CLK             0x04
#define ADC1_CFG_DELAY_GO_6_CPU_CLK             0x05
#define ADC1_CFG_DELAY_GO_7_CPU_CLK             0x06
#define ADC1_CFG_DELAY_GO_8_CPU_CLK             0x07

But I see table that shows that 0 is 1 clock.

Таблица 290 – Время заряда внутренней емкости АЦП и время преобразования

[eldarkg]

Where you found this bits:

/* Delay ADC Modes */
#define ADC1_CFG_DELAY_ADC_1_CPU_CLK            0x00
#define ADC1_CFG_DELAY_ADC_2_CPU_CLK            0x01
#define ADC1_CFG_DELAY_ADC_3_CPU_CLK            0x02
#define ADC1_CFG_DELAY_ADC_4_CPU_CLK            0x03
#define ADC1_CFG_DELAY_ADC_5_CPU_CLK            0x04
#define ADC1_CFG_DELAY_ADC_6_CPU_CLK            0x05
#define ADC1_CFG_DELAY_ADC_7_CPU_CLK            0x06
#define ADC1_CFG_DELAY_ADC_8_CPU_CLK            0x07
#define ADC1_CFG_DELAY_ADC_9_CPU_CLK            0x08
#define ADC1_CFG_DELAY_ADC_10_CPU_CLK           0x09
#define ADC1_CFG_DELAY_ADC_11_CPU_CLK           0x0A
#define ADC1_CFG_DELAY_ADC_12_CPU_CLK           0x0B
#define ADC1_CFG_DELAY_ADC_13_CPU_CLK           0x0C
#define ADC1_CFG_DELAY_ADC_14_CPU_CLK           0x0D
#define ADC1_CFG_DELAY_ADC_15_CPU_CLK           0x0E
#define ADC1_CFG_DELAY_ADC_16_CPU_CLK           0x0F

I see DelayADC[3:0] are reserved.

[eldarkg]

Where is defines eth buffer sizes in doc:

#define MDR_ETHERNET1_BUF_SIZE    8192
#define MDR_ETHERNET1_BUF_SIZE    8192

[eldarkg]

This was the my last question

[in4lio]

All changes come from "MDR1986VE1T.h". I should check and fix both headers.

[in4lio]

#define TIMER_CNTRL_CNT_MODE_UP_DOWN_DIR_AUTO_EVENT_1   0x03

It seeped from 1986ВЕ9x. Removed...

[in4lio]

// CCR1 EN = 1
...
#define TIMER_CH_CNTRL_OCCM_SW_REF_CNT_CCR              0x03

Renamed to TIMER_CH_CNTRL_OCCM_SW_REF_CNT_CCR_OR_CNT_CCR1 for "MDR32Fx.h", "MDR1986VE1T.h" and "MDR1986VE3.h"

[in4lio]

/* Delay ADC Modes */
#define ADC1_CFG_DELAY_ADC_1_CPU_CLK            0x00
...

Oops... not implemented in 1986ВЕ3 at all

[in4lio]

Where is defines eth buffer sizes in doc?

"Буфер 8 кБ" on the scheme:

[in4lio]

Done

[eldarkg]

@in4lio Sorry. Maybe we should to keep

#define ADC1_CFG_DELAY_GO_1_CPU_CLK             0x00

delete

#define ADC1_CFG_DELAY_GO_0_CPU_CLK             0x00

see table

Таблица 290 – Время заряда внутренней емкости АЦП и время преобразования

I think it is typo in table

Таблица 293 – Описание бит регистра ADC1_CFG

[eldarkg]

Repeat: Where are this bits?

Таблица 269 – Описание бит регистра CNTRL
EVENT_SEL[3:0]:
4’b1001 – событие заднего фронта ETR
4’b1010 – CNT == ARR в таймере 4

[eldarkg]

Please revert in all files

#define ADC1_CFG_DELAY_ADC_1_CPU_CLK        0x00
#define ADC1_CFG_DELAY_GO_1_CPU_CLK         0x00

[in4lio]

Take a look, please.

[eldarkg]

Good work. Thank you