Clock inputs rating

[micbeldyga]

@gkasprow What's the required input rating for clock inputs? We've discussed clk inputs being "TTL compatible" but also decided to do TTL-to-LVPECL conversion using a resistive divider, to limit number of ICs adding jitter to the system.

MC100LVEP111 I selected for 1:8 fanout buffer has limit of Vi<Vcc. Vcc can be supplied with max 3.8V, Datasheet specifies Vin thresholds only 2.5V and 3.3V but notes that thresholds change 1:1 with Vcc.

TTL output, depending on the driver family, can range from 0V to 0.4V for Vout-l and 2.4V to 5V for Vout-h. If we assume that TTL Vout-h = 5V and set the divider to limit Vin to 3.8V, we need a division ratio of ~1.31.

For Vcc = 3.8V Vin-h threshold should be ~2635mV, which means that a clock signal with "1" level lower than 3450mV won't work (division ratio 1.31). For Vcc = 3.6V Vin-h threshold should be ~2435mV, which means that a clock signal with "1" level lower than 3381mV won't work (division ratio 1.38). For Vcc = 3.3V Vin-h threshold should be ~2135mV, which means that a clock signal with "1" level lower than 3234mV won't work (division ratio 1.51).

Unless I made a fundamental error with my reasoning we have to come up with a different way for TTL-to-LVPECL conversion, explicitly specify on the front panel expected input levels, or protect MC100LVEP111 inputs by clamping Vin to Vcc limit.

[gkasprow]

Just add 100Ohm series resistor and low capacitance Schottky diode to VCC. It will be 50Ohm terminated in most cases

[gkasprow]

• [x] there is an issue with driving NB3L553MNR4G from LVPECL output. The H level is fine, but in the case of logic L we have 3.3V-1.69V which is far higher than 3.3/2-0.7v

[gkasprow]

maybe go for https://www.analog.com/media/en/technical-documentation/data-sheets/6957fb.pdf It has sth about 60Ohm output resistance. With two outputs in parallel we would get 30Ohm. That is barely sufficient to drive 2.1V to 50Ohm

another option is NB3F8L3005C which has 20Ohm output resistance. We can run 3 outputs in parallel.

[gkasprow]

• [x] please add power budget

[gkasprow]

• [x] there are missing holes for mezzanine board - add 4 3.2mm holes and spacers

[gkasprow]

@micbeldyga

[micbeldyga]

another option is NB3F8L3005C which has 20Ohm output resistance. We can run 3 outputs in parallel.

Won't having 3 outputs tied together, with up to 25ps skew between them worsen the jitter? With 20Ω output resistance of a single output, we'd get ~2.35V into 50Ω load which should be sufficient for TTL input, assuming Vcc = 3.3V

[gkasprow]

I think we need series resistor or ptc fuse to make sure the driver will survive constant short to gnd. But singlw output and PTC would do the job.

[gkasprow]

I think we need cleaner 3V3 rail to get 1ps jitter performance. I'd add LDO at the DC/DC output. Just add LC filter then FB and then LDO https://electronics.stackexchange.com/questions/625078/how-to-filter-out-the-switching-noise-from-a-dc-dc-converter

[micbeldyga]

I agree, I'll add separate LDOs with filtering for MUX and Fanout sections