P5_MODE[2:0] is 0x2 not 0x1 (MII MAC not MII PHY)

elhep / AFCZ

AMC FMC Carrier board based on ZYNQ Ultra Scale + SoC

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P5_MODE[2:0] is 0x2 not 0x1 (MII MAC not MII PHY) #112

Closed marmeladapk closed 3 years ago

marmeladapk commented 3 years ago

Update note in ETH_PHY schematics.

Also @gkasprow is this the right mode for this port?

marmeladapk commented 3 years ago

Hmm, I made a table based on LPC and Marvell datasheets:

	LPC	Switch (mac mode)	Switch (phy mode)
rx_clk	input	input	output
tx_clk	input	input	output

@gkasprow Shouldn't switch be set to phy mode? Although I seem to recall that there was an issue with some components that fought over clock. Was this with switch and MMC?

marmeladapk commented 3 years ago

@wizath confirmed that switch should be set to PHY mode. So change P5_MODE1 to pulldown and P5_MODE0 to pullup.