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elhep / AFCZ

AMC FMC Carrier board based on ZYNQ Ultra Scale + SoC
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Flash memory for user data connected to PL #150

Closed kaolpr closed 3 years ago

kaolpr commented 3 years ago

CERN insists on having direct access to some non-volatile memory from PL to store WRC calibration data.

Please add a separate flash connected to PL exclusively and make it an assembly variant.

arthurspi commented 3 years ago

Concerning this issue our prefered solution is having PS and PL pins connected to the same flash. I.e. shorting the PS & PL pins (post the TXB0108 buffers). This prove to work on our boards and allows for flashing over PCIe.

filipswit commented 3 years ago

@arthurspi Is this solution fine for you? Should Enable be driven from MMC, to switch between PS and PL access?

image

arthurspi commented 3 years ago

@filipswit The idea is to have access to the flash that holds the board's firmware from the PL. We don't actually need a second memory. If we can apply the same circuit to the existing flash that would be perfect.

If there is a switching it should also be accessible from the PL.

filipswit commented 3 years ago

@arthurspi If you want to use flash that already exist (IC37 IC40), don't you have access to it through FPGA_SPI_FLASH_UPDATE?

arthurspi commented 3 years ago

@filipswit The reason is there is a shared infrastructure at cern to flash over PCI, and it has a direct SPI interface as for the wr-core. by FPGA_SPI_FLASH_UPDATE do you mean the axi interface?

filipswit commented 3 years ago

There is an SPI connected to MMC and PL. image image

arthurspi commented 3 years ago

To my understanding there is one SPI connection between the MMC and the PL but not between PL and the QSPI flash

filipswit commented 3 years ago

@arthurspi sorry, you are right, while making #84, just realized that there are two separate SPIs. I added another from PL to Flash.