I assume that both FPGA_SPI and FPGA_SPI_FLASH_UPD are connected to masters. Then port A1 of IC57 should transmit data in the other direction. Look at IC89 it seems to have proper directions set.
DIR1 to P1V8, DIR2 to GND or swap lines. (MOSI should have DIR to GND, MISO DIR to P1V8).
IC57 (SOC_PS_PSIO):
I assume that both FPGA_SPI and FPGA_SPI_FLASH_UPD are connected to masters. Then port A1 of IC57 should transmit data in the other direction. Look at IC89 it seems to have proper directions set.
DIR1 to P1V8, DIR2 to GND or swap lines. (MOSI should have DIR to GND, MISO DIR to P1V8).