Closed gyorka closed 2 months ago
Oh, the resistor on SPEC side are on wrong lines, FPGA Tx means input; Add them on Tx lines on your side
so I should also connect TX to RX port and vice versa?
No, follow Ethernet rules; Rx connects with Rx, Tx with Tx; use source ermination on your output signals
done
at spec_a7 fpga_34.schdoc there are 33R resistors at RGMII TX lines, should we add 33R resistors at RX lines here? or its already good as it is?