elhep / SpaceVPX_FMC_Carrier_3U

general purpose Space VPX 3U carrier for SDR radio
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SI verification #14

Closed tprzywoz closed 5 years ago

tprzywoz commented 5 years ago

Enable lossy simulation ON Enable surface roughness ON Loss tangent 0.02

DDR: 416 MT/s Timing models DDR_400 (correct for lpddr chip, couldn't find information about FPGA) Included crosstalk effects image image image image image

There is a problem with timing for data write. LPDDR has 480 ns setup and hold time. Margin has failed only because of high output variation (300 ps). Simulated setup and hold time is about ~750 ps. All signals have matched lengths rule with tolerance 0.1 mm.

tprzywoz commented 5 years ago

UTP: VPX connector uses fpga ami ibis model. 5 Gbps. image

tprzywoz commented 5 years ago

SpW. VPX connector again uses fpga models. 200 MHz image