Enable lossy simulation ON
Enable surface roughness ON
Loss tangent 0.02
DDR:
416 MT/s
Timing models DDR_400 (correct for lpddr chip, couldn't find information about FPGA)
Included crosstalk effects
There is a problem with timing for data write. LPDDR has 480 ns setup and hold time. Margin has failed only because of high output variation (300 ps). Simulated setup and hold time is about ~750 ps. All signals have matched lengths rule with tolerance 0.1 mm.
Enable lossy simulation ON Enable surface roughness ON Loss tangent 0.02
DDR: 416 MT/s Timing models DDR_400 (correct for lpddr chip, couldn't find information about FPGA) Included crosstalk effects
There is a problem with timing for data write. LPDDR has 480 ns setup and hold time. Margin has failed only because of high output variation (300 ps). Simulated setup and hold time is about ~750 ps. All signals have matched lengths rule with tolerance 0.1 mm.