Schematics design review

[gkasprow]

please generate schematics and post them here.

[ISlipukhin]

XMC_ZynQ_schematics_10_07.pdf

[gkasprow]

• [x] comparators are wired in the wrong way. Please review it. The input terminals must be exchanged.

[gkasprow]

• [ ] I talked today with guys who use this SoC in satellite designs. You cannot simply adjust thresholds for overcurrent. THere is Xilinx note on this. There are two kind of latchup events which need to be treated in different way. First kind of event results in slight increase of the supply current, especially on rails which do not consume much power. This is an order of tens of mA. The chip should be powered on, but there is a time for the OS to shutdown and save the context. The second kind of events results in rapid current increase. The power must be removed immediately. You assumed 10% current cut-off level over arbitrarly defined power level. This is wrong approacch. How do you know now what your level is? The current consumption also varies with temperature. So the levels must be adjusted close to the maximum allowable ones. The best approach would be to apply MSP430FR5969 which has also MSP430FR5969-SP radiation hardened variant. Such CPU would generate valid thresholds using PWM channels and also measure the current using its own ADC. In this way, the CPU can detect these subtle increases of the rail currents and notify the SoC to shut down.

[ISlipukhin]

Thanks for that information. Xilinx has not specified maximum allowable current consumptions for Zynq UltraScale+ devices yet. Now there is only some relevant data for Virtex UltraScale+ (UG583 p. 45). The current values that I have used in my calculations were obtained using Xilinx power estimator spreadsheet. I have tried to emulate maximum current consumption by enabling all system elements, including processors, programmable logic, DDR controller and MGTs operating at maximum speed. For programmable logic, I have specified the logic cells and block RAM ulilization required for SpaceFibre and White Rabbit IP cores implementation.

[ISlipukhin]

Here is the newest version of schematics (with CPU) XMC_ZynQ_schematics_13_08.pdf

[ISlipukhin]

PCB is also updated.

[gkasprow]

please do not update the PCB until we resolve all schematic issues.