Many newer STM32 use an "interesting" addressing scheme for their interrupt vectors. Namely, the EXTI13 handler's address does not match its position. For example, here's a small extract of the STM32H563's reference manual, page 703 (emphasis mine):
Position
Acronym
Address
21
EXTI11
0x94
22
EXTI11
0x98
23
EXTI12
0x9C
24
EXTI13
0xE4
25
EXTI14
0xA0
25
EXTI15
0xA4
However, embassy-stm32 will assume that all interrupt handlers' addresses are sequential in the vector table, and generate a vector table accordingly.
As a result, every single interrupt handler after the one for EXTI13 is incorrect (its address is off by one in the table).
This seem to apply to many newer Cortex-M33 based STM32s.
Many newer STM32 use an "interesting" addressing scheme for their interrupt vectors. Namely, the
EXTI13
handler's address does not match its position. For example, here's a small extract of the STM32H563's reference manual, page 703 (emphasis mine):However,
embassy-stm32
will assume that all interrupt handlers' addresses are sequential in the vector table, and generate a vector table accordingly.As a result, every single interrupt handler after the one for
EXTI13
is incorrect (its address is off by one in the table).This seem to apply to many newer Cortex-M33 based STM32s.